[Paper Review] A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8Architecture

 

 

 

A Portable and Fault-Tolerant Microprocessor Based on the SPARC V8 Architecture

https://ieeexplore.ieee.org/document/1028926

A portable and fault-tolerant microprocessor based on the SPARC v8 architecture

 

 

 

ABSTRACT

 The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors tolerates transient SEU errors by using techniques such as TMR registers, on-chip EDAC, parity, pipeline restart, and forced cache miss.

 The first prototypes were manufactured on the Atmel ATC35 0.35 µm CMOS process, and subjected to heavy-ion fault-injection at the Louvain Cyclotron. The heavy-ion tests showed that all of the injected errors (> 100,000) were successfully corrected without timing or software impact. The device SEU threshold was measured to be below 6 MeV while ion energy-levels of up to 110 MeV were used for error injection. 

 

 

 

INTRODUCTION

 In 1997, the European Space Agency (ESA) completed the development of a 32-bit microprocessor for embedded space-flight applications, denoted ERC32 [1]. The ERC32 is based on the Cypress CY601 SPARC V7 processor and is now being used in several space projects, including the control computers of the International Space Station. 

 To meet the mission requirements for projects beyond year 2000, the development of a new and improved processor denoted LEON was started in 1998. This paper presents the design goals, architecture, built-in fault-tolerance functions and initial test results of this processor. The LEON project was started by ESA under the Douglas Marsh fellowship and the ESA Technology Research Programme (TRP), and is now continued by Gaisler Research under ESTEC contract 15102/01/NL/FM.

 

 

 

The objective for the LEON processor

1. Use of commercial semiconductor process. To reduce cost and increase performance, it should be possible to implement the processor on commercial, single-event upset (SEU) sensitive semiconductor processes.

 

2. Portability. To guarantee long-term availability, the processor should be portable across wide range of semiconductor processes with minimum cost and effort, while maintaining functionality and performance.

 

3. Modularity. The processor implementation should allow reuse in system-on-a-chip (SOC) designs.

 

4. Scalability. The processor should be usable in both low-end and high-end applications with minimum hardware and software overhead. 

 

5. Standard interfaces. The processor should have standardized interfaces to simplify system integration and to reuse commercial cores, components and tools.

 

6. Software compatibility. The processor should be compatible with both the currently used ERC32 software development tools and COTS software packages.

 

 

 

 

 

 

컴구시간에 배웠던 파이프라인 개념.!

 

 

 

CONCLUSION

 Well-know error-detection and correction techniques such as parity, BCH and TMR have been used to implement an SEU-tolerant processor on a non-hardened semiconductor process. By choosing the appropriate detection and correction method for each specific memory type, the area overhead has been kept low.

 Fault-injection using heavy ions has proved the efficiency of the fault-tolerance concept, although some anomalies were detected at high particle fluxes. The portable design style and simple synthesis method insures long-term availability and quick access to new semiconductor processes.