SohyeonKim(347)
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[ํ์คํ] UDP - User Datagram Protocol
UDP User Datagram Protocol The User Datagram Protocol (UDP) is called a connectionless, unreliable transport protocol. It does not add anything to the services of IP except to provide process-to-process communication instead of host-to- host communication. If UDP is so powerless, why would a process want to use it? Very simple protocol using a minimum of overhead if a process wants to send a sma..
2023.04.11 -
[ํ์คํ] Transport Layer 4 / Process-to-Process Delivery
Process-to-Process Delivery The data link layer is responsible for delivery of frames between two neighboring nodes over a link. This is called node-to-node delivery. -> ์๋ก ๋ค๋ฅธ ๊ณ์ธต, ex) 1 - 2 ๊ณ์ธต ๊ฐ ์ฃผ๊ณ ๋ฐ์ ๋ The network layer is responsible for delivery of datagram between two hosts. This is called host-to-host delivery. -> ๋์ผํ ๊ณ์ธต๋ผ๋ฆฌ ์ฃผ๊ณ ๋ฐ์ ๋ (host) ์์ ์ดํด๋ณธ 1,2 ๊ทธ๋ฆฌ๊ณ 3 ๊ณ์ธต ์ด์ผ๊ธฐ The transport layer is respons..
2023.04.11 -
[์ด์์ฒด์ ] CFS in Linux
CFS Completely Fair Process Scheduling in Linux
2023.04.10 -
[ํ์คํ] 3 Layer Router, IP address, DNS
Packetizing packetizing -> ์์์ ๋ฐ์ ๊ฒ์, ๋ณธ์ธ์ด ํด์ผํ ์ผ, ์ฆ ์ ๋ณด๋ฅผ ๋ฃ๋๋ค. Encapsulating the payload in a network- layer packet at the source and decapsulating the payload from the network-layer packet at the destination In other words, one duty of the network layer is to carry a payload from the source to the destination without changing it or using it. The network layer is doing the service of a carrier such..
2023.04.08 -
[ํ์คํ] CSMA/CD _ Random Access Protocols in MAC Layer
CSMA / CD (์ด๋๋ท, ์ด๊ณ ์ ์ธํฐ๋ท, ๊ด ๋, IEEE 802.3) Carrier Sense Multiple Access with Collision Detection (CSMA/CD) augments the algorithm to handle the collision. In this method, a station monitors the medium after it sends a frame to see if the transmission was successful. If so, the station is finished. If, however, there is a collision, the frame is sent again. ํ ์ค์ ์ฌ๋ฌ ๋ช ์ด ๋์์ ์ฌ์ฉํ๋ค. ์๊ธฐ ์ ์ ๋๊ฐ ์๊ณ ์๋์ง ํ์ธ..
2023.04.08 -
[ํ์คํ] OSI 7 Layer
* OSI 7 Layer ์ปดํจํฐ ์ํํธ์จ์ด์ ํ๋์จ์ด๋ฅผ ํต์ ๊ด์ ์์ ์ดํดํ๋ ๋ชจ๋ธ The Open Systems Interconnection model (OSI model) is a conceptual model that characterizes and standardizes the communication functions of a telecommunication or computing system without regard to its underlying internal structure and technology. Its goal is the interoperability of diverse communication systems with standard protocols. The model pa..
2023.04.08 -
[์ด์์ฒด์ ] GPGPU for Deep Learning 2023.04.02
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[์ด์์ฒด์ ] CPU Interrupt
Interrupt handler - ์ธํฐ๋ฝํธ๋ฅผ ํด๊ฒฐํ๋ func - ISR (interrupt service routine) - ์ธํฐ๋ฝํธ ๋ฐ์! -> ์ด์์ฒด์ ๊ฐ ์ํ๋จ โญ๏ธ ์ธํฐ๋ฝํธ์ 3๊ฐ์ง ์ข ๋ฅ 1) Interrupt - Hardware interrupt - asynchronous - ๋น๋๊ธฐ๋ก ์ฒ๋ฆฌ๋๋ค. - CPU๋ ์ด ์์ (์ธํฐ๋ฝํธ)๋ฅผ ๊ธฐ๋ค๋ฆฌ์ง ์๋๋ค -> ๋ค๋ฅธ ์์ ์ํ -> ๋ค์ ๋์์ด == acync - ex) ํค๋ณด๋ ์ธํฐ๋ฝํธ, timer interrupt 2) Trap - Software interrupt - Application process - Sync ๋๊ธฐ์ ์ผ๋ก ์ฒ๋ฆฌ๋๋ค. - ex) System Call -> App์ด ๋์คํฌ์์ ๋ฐ์ดํฐ ์ฝ์ด๋ฌ๋ผ๊ณ OS์๊ฒ ๋์ ์์ฒญ (์บก์ํ, ์ธํฐํ์ด์ค ..
2023.03.25 -
[์ด์์ฒด์ ] CPU์ Architecture _ SMP vs NUMA vs Clustered system
Bootstrapping in Linux - CPU - smart X -> ๋งค์ฐ ๋น ๋ฅด๊ฒ ๋ฉ๋ชจ๋ฆฌ์์ ๋ช ๋ น์ด๋ฅผ ์ฝ๊ณ , ์คํํ๋ ๊ฒ - ROM - Read only memory - ์ฝ๊ธฐ ์ ์ฉ ๋ฉ๋ชจ๋ฆฌ, ์๊ตฌ์ ์ผ๋ก ์ ์ฅํ๋ ๋นํ๋ฐ์ฑ ๋ฉ๋ชจ๋ฆฌ - ์ ์์ด ๊บผ์ ธ๋ ์กด์ฌ -> ์ฒ์ ๋ถํ ๋ ๋ ์คํํ ๋ชจ๋ + RAM - Random Acess Memery - ํ๋ฐ์ฑ ๋ฉ๋ชจ๋ฆฌ, ์์ ์ค์ธ ๋ด์ฉ์ ํ์์ ์ผ๋ก ์ ์ฅ ํ๋์จ์ด ์ด๊ธฐํ ๋ฐ ํ ์คํธ - BIOS - Basic input output system - UEFL - Unified Extensible Firmware Interface -> ํ์จ์ด : ํ๋์จ์ด์ ํฌํจ๋ ์ํํธ์จ์ด == ๋กฌ์ ์ ์ฅ๋ ์ํํธ์จ์ด -> POST - power on self test ์งํ - ๋ฉ๋ชจ๋ฆฌ ๋ฐ i..
2023.03.25 -
[์ด์์ฒด์ ] ์ปดํจํฐ ๊ตฌ์กฐ ๋ฐ ์ด์์ฒด์ ๊ฐ์ / Kernel / System Call
์ด์์ฒด์ (Operating System)๋? - ์ปดํจํฐ ํ๋์จ์ด(CPU, IO์ฅ์น, ๋ฉ๋ชจ๋ฆฌ) ์์ ์ปดํจํฐ ์ํํธ์จ์ด๊ฐ ์ํ๋๋๋ก ๊ด๋ฆฌํด์ฃผ๋ ์ํํธ์จ์ด - ํ๋ก๊ทธ๋จ์ด ํ๋์จ์ด๋ฅผ ๋ชฐ๋ผ๋ ์ฝ๊ฒ ์ฌ์ฉํ ์ ์๋๋ก ์ธํฐํ์ด์ค ์ ๊ณต -> ์์คํ ์ฝ - CPU์ ๊ฐ์ ํ๋์จ์ด๊ฐ ํจ์จ์ ์ผ๋ก ์ฌ์ฉ๋๋๋ก ๊ด๋ฆฌ - ํ๋์จ์ด ๋ด๋ถ์์ ๋ฐ์ดํฐ๋ฅผ ์ฃผ๊ณ ๋ฐ๋ ํต๋ก - BUS 1) System controller (north Bridge) - CPU, ๋ฉ๋ชจ๋ฆฌ(DRAM), ๊ทธ๋ํฝ ์นด๋(AGP) - memory controller hub (MCH) - ๋งค์ฐ ๋น ๋ฅธ ์๋๊ฐ ์๊ตฌ๋จ - AGP Bus, Memory Bus 2) Pheripheral Bus (South Bridge) - I/O Controller Hub - LAN, USB, ํค..
2023.03.25